George Toms synthesis
7 segment octal decoder
Design Parameters:
Max. gates
Design Parameters:
Project name:
7 segment octal decoder
Input names, input vectors:
A,B,C
00001111,00110011,01010101
Output names, output vectors:
a,b,c,d,e,f,g
Output orders:
original
reverse
reverseBut0
Gates sets and (pole accelerators):
nand4,nor4,and4,or4,xor2,xnor2 (0,2,3)
nand3,nor3,and3,or3,xor2,xnor2 (0,2)
nand2,nor2,and2,or2,xor2,xnor2 (0)
nand4,nor4,xor2,xnor2 (0,2,3)
nand3,nor3,xor2,xnor2 (0,2)
nand2,nor2,xor2,xnor2 (0)
nand4,nor4,and4,or4 (0,2,3)
nand3,nor3,and3,or3 (0,2)
nand2,nor2,and2,or2 (0)
nand4,nor4 (0,2,3)
nand3,nor3 (0,2)
nand2,nor2 (0)
nor4 (0,2,3)
nor3 (0,2)
nor2 (0)
nand4 (0,2,3)
nand3 (0,2)
nand2 (0)
Optimization:
delay
gates
transistors
area
power
fan-out
levels
wires
none
Gates:
Truth Table:
Truth Table:
Export Truth Table to LF
Design results:
Design results:
Selected Gate-Level Netlist:
Show Netlist
Gate-Level Netlist:
Gate-Level Netlist:
Export to Verilog and VHDL
Export Netlist
Show Schematic
Export Schematic
Show Racing
Schematic:
Schematic:
Racings:
Racings:
